1. Technical Field
The present invention relates generally to an improved data processing system and in particular to a method and apparatus for arbitrating access to multiple buses in a data processing system. Still more particularly, the present invention relates to a method and apparatus for arbitrating access to multiple buses in a data processing system using a distributed arbitration mechanism.
2. Description of the Related Art
The performance demands on personal computers are ever increasing. It has been determined that a major bottleneck in improving performance is the capability to perform input/output (I/O) operations. Processor speeds continue to increase at a great rate and memory speeds and architectures can partially keep pace. However, the speed of I/O operations, such as disk and local area network (LAN) operations, has not kept pace. The increasing complexity of video graphics used in personal computers is also demanding greater performance than can be conventionally provided.
Some of the problems were in the bus architecture used in IBM PC-compatible computers. The EISA architecture provided some improvement over the ISA architecture of the IBM PC/AT, but more performance was still required. To this end Intel Corporation, primarily, developed the Peripheral Component Interconnect (PCI) bus. The PCI bus is a mezzanine bus between the host or local bus in the computer, to which the processor and memory are connected, and the I/O bus, such as ISA or EISA. For more details on the PCI bus, reference to the PCI Standard Version 2.0, from the PCI Special Interest Group in care of Intel Corp., which is hereby incorporated by reference, is advised. The bus was designed to have a high throughput and to take advantage of the increasing number of local processors that support I/O functions. For example, most disk controllers, particularly SCSI controllers, and network interface cards (NICs) include a local processor to relieve demands on the host processor. Similarly, video graphics boards often include intelligent graphics accelerators to allow a higher level function transfer. Typically these devices have the capability of operating as bus masters, to allow the devices to transfer data at the highest possible rates. Each of these devices also is referred to as a "node".
To effectively utilize a common bus system for the transfer of data and messages by various local processors connected to the bus some form of arbitration is required to determine which processor obtains access to the bus. A central arbiter may be coupled to each of the processors to determine which one will be granted access to the bus during any given bus cycle. Such a central arbiter receives separate bus requests from various nodes at times when those nodes are ready to obtain access to a bus to transmit a message or transfer data to another node. In response to a number of bus requests, the central arbiter sends a bus grant to only one of the requested nodes in a predetermined matter corresponding to a selected priority scheme.
In data processing systems containing multiple buses and multiple master devices, in which the master devices communicate with devices on other buses, a system of arbitration on multiple buses is required for high performance and reliability of avoiding deadlock situations in which master devices on different buses make requests for target devices or resources on opposite sides of the buses. Presently available arbitration systems include a complex hierarchical arbitration system that determines all possible deadlock situations up front in designing the system. In such an arbitration system, all of the deadlock situations are designed into a top level arbiter. This top level arbiter, directed lower level arbiters on the bus level to avoid deadlock. The drawback of such an arbitration system is that is a potential deadlock condition was missed, the chip could lock up. Therefore, an improved method and apparatus for bus arbitration that avoids deadlock situations for multiple bus data processing systems is desirable.